1. Field of the Invention
The present invention relates to a semiconductor package, and more particularly, to a semiconductor package structure that has low power supply inductance.
2. Description of the Prior Art
Memory, such as DRAM and logic devices are commonly used in modern computers and electronic products. These memory devices are usually packaged as a semiconductor chip. An exemplary DRAM package consists of a semiconductor DRAM die mounted under a single layer substrate. This is commonly known as a Board-on-Chip (BOC) design. One side of the die comprises a plurality of bond pads and can be referred to as a circuit side. The substrate also has a circuit side comprising a plurality of internal conductive traces and a plurality of external contacts in the form of power supply soldering balls, which communicate electrically with the traces on the substrate. The DRAM package is formed by bonding the circuit side of the die to the backside (non-circuit side) of the substrate. Traces are then coupled to the bond pads using wire bonds. Other package configurations are Chip-on-Board (COB) designs and Fine Ball Grid Array (FBGA) designs, both also have the same concept of power supply balls coupling to bond pads. In the following description, reference will be made to the BOC design for brevity.
Please refer to FIG. 1A, FIG. 1B and FIG. 1C, which represent, respectively, a top view, a first side view and a second side view of a conventional BOC DRAM package 10. FIG. 1A shows a package substrate 15 comprising a number of power supply balls 22, 24, 26 and a DRAM die 30 (represented by the dashed outline). The substrate 15 is rectangular in shape with a hollow middle section that exposes the die 30 underneath. The die 30 has a number of bond pads 32, 34, 36 located on the centre section of the die 30 which are exposed through the hollow middle section of the package substrate 15 as shown in FIGS. 1A and 1C. The first side view, shown in FIG. 1B, shows the package substrate 15 bonded to the die 30 from an end perspective and also shows the power supply balls including the power supply ball 26 on the circuit side of the package substrate 15. In FIG. 1C, the wire bonding between the package substrate 15 and the bond pad 32 on the die 30 is shown. Wire bond 42 couples the bond pad 32 to conductive traces (not shown) in the package substrate 15, which in turn are coupled to the power supply ball 22. The wire bonding is only from the circuit side of the substrate 15 to the circuit side of the die 30.
Please refer to FIG. 2 for a circuit-level illustration of the connections between the bond pads and the power supply balls. The diagram shows a single output circuit for simplicity, comprising an output driver coupled between two power supply balls 24, 26, respectively coupled to VSSQ and VDDQ with the output voltage DQ_Out being output through a third power supply ball 22 which is coupled between VDDQ_EXT and VSSQ_EXT (ground). Power supply balls 24, 26 are respectively coupled to bond pads 34, 36, and power supply ball 22 is coupled to bond pad 32. The current is pulled and pushed between VSSQ and VDDQ, and the switching results in a considerable amount of inductive Simultaneous Switching Output (SSO) Noise on the power supply rails.
One method to reduce this inductance is to increase the thickness of the bonding wires. This is not very effective, however, as the number of bonding wires that can be used is limited by the space available in the package. Modern designs tend to have a congested routing environment; using thicker wires would therefore involve increasing the size of the substrate, which is unlikely to provide an effective solution to high speed SSO noise reduction. Modern high speed I/O package designs require a minimized power supply inductance in conjunction with a small substrate size.